the cpu chip that maps physical memory (up to 1M byte)
Actually, the physical address range is 2megabytes. The hucard games have only uses the lower 1megabyte, but the hucard port itself is the full 2megabyte range. It's how the Arcade card maps into its registers into bank $FF at location $1a00-1aff. There's lots of other free/open bus space in the upper 2megabyte range as well. I think it's just that NEC reserved it for back end peripherals for developers, but that's only by choice - not function. With a tiny bit of glue logic and no mapper required, you could technically make a 12megabit hucard (and bigger too). IIRC, banks $88 to $F6 are open bus. And bank $F8 has open bus from $1c00 to $1ffff still open, after the arcade takes what it needs (great for mapping in new hardware device registers).
what an MPR is
I forget what it stands for. But the R stands for Register. Though we tend to say MPR register, which is redundant. Probably MaPper Register. The cpu has a logical address range and a physical address range. Unlike the original line of 65x CPUs that only have 16bit physical (64k) and logical (64k) address ranges, the PCE's 6280 has 16bit logical and 21bit external address ranges(2048k or 2megabytes or 16megabits). This means there's not need for additional hardware like external mappers to get past the physical address limitations (like NES or A8 or C64, etc). Anyway, the logical address range is 16bit or 64k. This 64k is divided neatly into 8 segments of 8k. So $0000-$1fff, $2000-$3fff, etc. The stack pointer register is an indexing register, but the base address for the STACK itself is fixed at location $2100 of logical address range. So no matter what you have mapped there, it will try to read or write from $2100 to $21ff range (8bit index). Some other things are fixed in location too. Zeropage (these are basically Address registers for any other type of processor and general purpose as well, with one distinction that they exist external to the CPU. Makes is cheaper for the CPU, though at a cost of an additional cycle or two - but the amount of registers (especially Addressing) is increased dramatically) is fixed at $2000-$20ff logical range. All the interrupt vectors reside in $fff6-$ffff logical address range. So, ram needs to exist at least at $2000-21fff range for ZP and STACK to work correctly (disregarding all-rom-mode and writing special code for that setup, waaaaaaaay beyond the scope of this topic). So you have MPR 0 to MPR 7. MPR 0 being $0000-$1fff and MPR 7 being $e000 to $ffff. On power up, the only MPR mapped with a specific constant value is MPR 7. And it automatically mapped to physical address range $000000-$001fff. A game can put whatever addresses it wants for any of the 5 interrupt vectors, but Reset (start up code) should always have a logical address range of $e000-$fffff, since nothing else is guaranteed to be mapped. If you don't use BRK for anything, you could always use it as a generic bug trapping feature. And if you put the same address value as the Reset vector, then you'll just get a restart (although game code could easily be made to look at ram and see if it's been previously initialized with an ID string, and thus call an output message. Or do nothing at all and just let the game reset. No fun to the gamer either way).
I digress a bit, but it would have been nice to have just a few special long address opcodes. Easy enough, since mapping is all handled internally. Even opcodes specifically for transferring values from the Acc register between the MPR registers (they're cpu based). MPR<n>+PC address mode, 24bit direct addressing (similar to paging on the x86). But oh well, it's not needed for speed - just convenience. And I always find something to rant about that's "should have been added".
