I could be wrong, but I thought I remembered a bug in mednafen when using vram break points (read/write) and the cpu's Txx instruction. If the vram address breakpoint is aligned with the first vram read or write of the Txx instruction, then no there's problem. But if the vram breakpoint address is somewhere after the initial write of the Txx instruction, but within the range of the block transfer, it won't trigger. As if the debugger only checks vram write/read once per cpu instruction initial read/write to the port, rather than any direct access of the vram address itself (speed reasons?). It's been a quite awhile since I've used it, but I'm pretty sure that was an issue.