TenNoKoe 2 - Full Component Guide (Including PCB Schematic)

[Fidde_se]

PCB Drawings:

Large http://www.retrosampling.se/Temp/TNK2/1.png


Large http://www.retrosampling.se/Temp/TNK2/2.png


Large http://www.retrosampling.se/Temp/TNK2/3.png

Components:
http://www.retrosampling.se/Temp/TNK2/TenNoKoe2%20Components.txt

PDFs:
http://www.retrosampling.se/Temp/TNK2/TenNoKoe2pdf.rar

[wolfman]

Cool work!

It doesn´t belong here, but do you happen to know if it is possible to measure voltage of the backup battery on the Tennokoe Bank Card without opening it?

[wilykat]

Cool work!

It doesn´t belong here, but do you happen to know if it is possible to measure voltage of the backup battery on the Tennokoe Bank Card without opening it?

I realize this is old thread but the backup batteries used in Ten No Koe 2 is a pair of 'AA' or LR6 batteries.  So around 3v when working good.

The HuC 6201 is the only chip that can't be sourced currently as it is propriety and I doubt anyone can get new one today. Maybe if someone could reverse engineer this one chip, they could build a compatible FPGA or CPLD interface to handle the memory, and use a 2k NVRAM instead of SRAM with convoluted battery watchdog circuit?  Hello, built in save support in Turbo Express!!

[wilykat]

/gravedigging

I was looking into this to try and draw up a schematic. I have 2 Tennokoe 2s to play with, and I intended to try and shoehorn one inside a Turboexpress someday.

I noticed one major error with the outline: in black outline for both images the SRAM chip is upside down!  The chip's notches side (which tells where pin 1 is) should be close to ext connector, not on the back away from the ext connector.

It's the only mistake I found so far.  And theorectally I can fit this inside a TE or GT once I find all the required address and data pins and /rst line.  I am trying to get rid of most of the components on the battery side to reduce the board to just 2 ICs and a few caps. If there is some room inside the TE, my idea is to use a 5v 1F cap (not uF, whole farad) on SRAM's Vcc and a diode from that to main 5v bus so the cap can be charged during normal use but would power only the SRAM when the system's off. The diode will prevent cap from powering the whole TE.

I am still checking into those 2 components that NEC chip connects to see what the function is (battery level check?) and see if those can be bypassed or faked.

[wilykat]

Update: those 2 can probably be bypassed.  IC3 is 2.5v detection, if the battery went low it would turn off the output of IC3 and pull pin 46 of the NEC chip low, which could be used to signal weak or dead battery warning.  Tie pin 46 to vcc to lock it up and leave IC3 out.

TR1 stands between pin 60 of NEC chip to /CE of SRAM. The base of the transistor is connected to IC4. My guess is if the volt goes below 3.9v (such as when system is OFF), it cuts off transistor and with a resistor to battery's +, this holds /CE line high and prevents SRAM from becoming active. We can probably bypass this and connect 60 directly to /CE of SRAM.  When IC4 is "on" and TR3 is "running", the NEC chip can control /CE line to enable or disable the SRAM chip.

One more pin of NEC chip connects through a resistor to cathode of LED, anode is connected to vcc. We can also skip this and reduce a whopping 20mA from TE's total consumption.

All that's left is to find all the important spots (address, data, /rst, etc) inside TE and see if I can get all of them to match up with the ext connector that is used by the battery unit.

If this can work, it'd mean I can play Neutopia and not be shafted by tiny letters in password screen.

[Fidde_se]

Fixed, checked my original files and it was correct, problem lays in that SMD is in bottom layer and silkscreen is top layer, and the silkscreen becomes like a see through and then everything becomes mirrored on the silk and all text has to be manually corrected each by each, and at some point the text for IC2 and the components layout has been mirrored at the same time.