Essentially, your TEOS support for extended memory mappers is the neatest solution I can imagine if you have a TED v.2, but having read some old posts refering to the SF2 Memory mapper and the challenges it presented it makes me wonder if it could be possible to considering an Arcade card mapping emulation on TEOS as you've done with SSC.
It just isn't possible. The Arcade Card memory is accessed in a totally different way to normal memory.
The TED v2 was just never designed to have those capabilities.
The TED v2 does emulate the SF2 mapper, and you can use all of that memory as RAM if you wish.
Accessing more than 2.5MB is also possible using the TED v2's built-in mapper, but that is very different to using the SF2 mapper.
PCEAS has included support for developing homebrew for the SF2 mapper (up to 8MBytes) since earlier this year, but nobody has used it yet AFAIK apart from my asm example project.
HuC will *never* natively support HuCARDs larger than 1MB because its program structure just isn't compatible.
I guess that the fact of TEOS requiring v2.5 ED was because of the use of a more capable CPLD of the latter (Lattice) vs Altera MAXII epm240t100c5n from previous versions, but as I stated, I am not versed in Verilog to see if there might even be enough macrocells available to consider implementing something of this complexity with the current available space.
TEOS's existence has nothing to do with the CPLD/FPGA size as such, it was possible because the TED v2 is built using 4MB of RAM, wheras the TED v1 was built using 1MB Flash-ROM.
Now, Krikzz probably couldn't have designed the TED v2 to use RAM without using the larger and more complex FPGA, but that's not quite the same thing. TEOS does not use or change the CPLD, it just uses the capabilities that Krikzz designed into the TED v2 and then documented.